1. Field of the Invention
The present invention relates to a method of producing a hetero-junction bipolar transistor widely used for a transmitting high-output power amplifier.
2. Related Background Art
A Hetero-junction Bipolar Transistor (hereinafter, HBT will be referred to) is a bipolar transistor including an emitter-base junction made of different semiconductor materials, wherein the band-gap of the emitter layer is larger than that of the base layer. As compared with a field-effect transistor (FET), an HBT is more desirable in that it can be operated with a single power source, the number of parts can be reduced, and various properties such as high gain and low distortion, and the like, are achieved. Applications for HBTs are expected to be broadened as a device of a transmitting high-output power amplifier used as a part of a cellular phone.
An HBT is produced by successively laminating semiconductor layers, mainly gallium arsenide (GaAs)-based semiconductor layers, by epitaxial growth on a semi-insulating substrate and by wet etching the laminated semiconductor layers to form an emitter layer, a base layer and a collector, separately. For the emitter layer, an n-type InGaP layer is used in general, which has less current carrying degradation and higher reliability as compared with AlGaAs. In addition, electrodes including TiPtAu, AuGeNi, etc. are connected to the formed emitter, base and collector layers.
FIG. 2 is a cross-sectional view showing a structure of a general HBT in which semiconductor layers are laminated by epitaxial growth. On one surface of a semi-insulating substrate 1 of a group III-V compound semiconductor material, a subcollector layer 2 including n+-type GaAs [impurity concentration: 5xc3x971018 cmxe2x88x923, film thickness: approximately 600 nm], a collector layer 3 including n-type GaAs [impurity concentration: 5xc3x971016 cmxe2x88x923, film thickness: approximately 600 nm], a base layer 4 including p-type GaAs [impurity concentration: 4xc3x971019 cmxe2x88x923, film thickness: approximately 100 nm], an emitter layer 5 including n-type InGaP [impurity concentration: 3xc3x971017 cmxe2x88x923, film thickness: approximately 30 nm] and an emitter cap layer 6 including n+-type GaAs [impurity concentration: 5xc3x971018 cmxe2x88x923, film thickness: approximately 400 nm] are laminated successively by the metal-organic chemical vapor deposition method (hereinafter, MOCVD method will be referred to), etc.
FIG. 3 is a cross-sectional view showing a device structure of a general HBT. In the semiconductor layers formed as mentioned above, a WSi (tungsten silicide) layer 10 is formed on the emitter cap layer 6 as an electrode layer for improving the reliability. Further on the WSi layer 10, an emitter electrode 8 (made of TiPtAu) connecting to wiring is formed. Furthermore, on the base layer 4, a base electrode 7 (made of TiPtAu) is formed in a region formed by etching the emitter layer 5. Furthermore, on the subcollector layer 2, a collector electrode 9 (made of AuGeNi/Au) is formed in a region formed by etching the subcollector layer 2 and the collector layer 3.
FIGS. 4A to 4F show steps of a conventional method of producing an HBT device. Firstly, as shown in FIG. 4A, on the emitter cap layer 6 of the device structure formed as mentioned above, a WSi layer 10 provided underside the emitter electrode 8 is formed by sputtering. Thereafter, a resist 100 is patterned so as to shape cells 20 as shown in FIG. 4E. Furthermore, by reactive ion-beam etching (hereinafter, RIE will be referred to) using CF4 and SF6 gas, the shape of the WSi layer 10 is adjusted under the conditions of in-chamber pressure of 100 mTorr and RF of 120 W.
Next, as shown in FIG. 4B, the shape of the emitter cap layer 6 is adjusted by wet etching using a phosphoric acid-based etchant containing phosphoric acid, hydrogen peroxide solution, and water in the ratio of 4:1: 45. This wet etching is carried out for a rather longer time, that is, when the thickness of the emitter cap layer 6 is, for example, 400 nm, the etching is carried out for the time assuming that the thickness is about 450 nm. At this time, depending upon the above-mentioned phosphoric acid-based etchant, the emitter layer 5 is not removed and only a part of the emitter cap layer 6 is removed, and thus a so-called selective etching is carried out. At this time, the hydrogen peroxide solution contained in the above-mentioned etchant acts as an oxidizer, and as a result, a thin surface oxidized layer 50 is formed on the surface of the emitter layer 5. Furthermore, at this time, the WSi layer 10 partially protrudes from the ends of the top portion of the emitter cap layer 6 by so-called side etching so as to form eave portions 10a. 
Next, as shown in FIG. 4C, the eave portions 10a are removed by RIE using only SF6 gas under the conditions of in-chamber pressure of 300 mTorr and RF of 100 W.
Next, as shown FIG. 4D, the resist 100 is removed, and then as shown in FIG. 4E, the shape of the emitter layer 5 is adjusted by wet etching using a hydrochloric acid-based etchant containing hydrochloric acid, phosphoric acid and water in the ratio of 3:2:2 so as to form the cells 20.
At this time, the cells 20 are formed on a chip at intervals of about 10 xcexcm with significantly high densities. Therefore, in the region around the cells 20, the etchant cannot circulate sufficiently. Furthermore, since the emitter layer 5 containing an element P of group V is covered with the surface oxidized layer 50 that was formed when the wet etching was carried out using the phosphoric acid-based etchant, a part of the emitter layer 5 is not removed by the above-mentioned hydrochloric acid-based etchant and remains in the form of a ring.
As shown in FIG. 4F, since a region in which the collector electrode 9 is to be disposed is formed in this state, when the wet etching is carried out on the base layer 4 and the middle portion of the collector layer 3 by using a phosphoric acid-based etchant, the areas of the emitter layer 5, the base layer 4, and the collector layer 3 are formed larger than the designed values, which may cause the property abnormality in that, for example, the amplification factor xe2x80x9chfexe2x80x9d of grounded emitter current of the HBT does not become a designed value.
It is an object of the present invention to produce an HBT having predetermined properties by resolving the problem that the amplification factor xe2x80x9chfexe2x80x9d of grounded emitter current of an HBT does not become a designed value because of etching defectiveness of the emitter layer including an element P in group V.
According to the present invention, when a hetero-bipolar transistor is produced, a surface oxidized layer formed on the emitter layer including an element P of group V is removed efficiently and semiconductor layers are formed as designed by resolving etching defectiveness, and thus HBTs having predetermined properties can be produced stably.